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| ? motorola, inc. 1994 prepared by: garth nash applications engineering abstract the fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. the necessary equations required to evaluate the basic loop performance are given in conjunction with a brief design example. introduction the purpose of this application note is to provide the electronic system designer with the necessary tools to design and evaluate phase-locked loops (pll) configured with integrated circuits. the majority of all pll design problems can be approached using the laplace transform technique. therefore, a brief review of laplace is included to establish a common reference with the reader. since the scope of this article is practical in nature all theoretical derivations have been omitted, hoping to simplify and clarify the content. a bibliography is included for those who desire to pursue the theoretical aspect. parameter definition the laplace transform permits the representation of the time response f(t) of a system in the complex domain f(s). this response is twofold in nature in that it contains both transient and steady state solutions. thus, all operating conditions are considered and evaluated. the laplace transform is valid only for positive real time linear parameters; thus, its use must be justified for the pll which includes both linear and nonlinear functions. this justification is presented in chapter three of phase lock techniques by gardner. 1 the parameters in figure 1 are defined and will be used throughout the text. figure 1. feedback system q i (s) q e (s) g(s) q o (s) h(s) + q i (s) phase input q e (s) phase error q o (s) output phase g(s) product of the individual feed forward transfer functions h(s) product of the individual feedback transfer functions using servo theory, the following relationships can be obtained. 2 ( 1 ) e (s) 1 1 g(s) h(s) i (s) o (s) g(s) 1 g(s) h(s) i (s) ( 2 ) these parameters relate to the functions of a pll as shown in figure 2. figure 2. phase locked loop f i q i (s) phase detector q o (s) programmable counter ( n) q e (s) filter vco/vcm f o q o (s)/n f o n order this document by AN535/d semiconductor application note rev 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2 motorola semiconductor application information the phase detector produces a voltage proportional to the phase difference between the signals q i and q o /n. this voltage upon filtering is used as the control signal for the vco/vcm (vcm voltage controlled multivibrator). since the vco/vcm produces a frequency proportional to its input voltage, any time variant signal appearing on the control signal will frequency modulate the vco/vcm. the output frequency is f o = n fi ( 3 ) during phase lock. the phase detector, filter, and vco/vcm compose the feed forward path with the feedback path containing the programmable divider. removal of the programmable counter produces unity gain in the feedback path (n = 1). as a result, the output frequency is then equal to that of the input. various types and orders of loops can be constructed depending upon the configuration of the overall loop transfer function. identification and examples of these loops are contained in the following two sections. type e order these two terms are used somewhat indiscriminately in published literature, and to date there has not been an established standard. however, the most common usage will be identified and used in this article. the type of a system refers to the number of poles of the loop transfer function g(s) h(s) located at the origin. example: let ( 4 ) g(s) h(s) 10 s(s 10) this is a type one system since there is only one pole at the origin. the order of a system refers to the highest degree of the polynomial expression 1 + g(s) h(s) = 0 d c.e. ( 5 ) which is termed the characteristic equation (c.e.). the roots of the characteristic equation become the closed loop poles of the overall transfer function. example: ( 6 ) g(s) h(s) 10 s(s 10) then 1 g(s) h(s) 1 10 s(s 10) 0 ( 7 ) therefore c.e. = s(s +10) +10 ( 8 ) c.e. = s 2 + 10s + 10 ( 9 ) which is a second order polynomial. thus, for the given g(s) h(s), we obtain a type 1 second order system. error constants various inputs can be applied to a system. typically, these include step position, velocity, and acceleration. the response of type 1, 2, and 3 systems will be examined with the various inputs. q e (s) represents the phase error that exists in the phase detector between the incoming reference signal q i (s) and the feedback q o (s)/n. in evaluating a system, q e (s) must be examined in order to determine if the steady state and transient characteristics are optimum and/or satisfactory. the transient response is a function of loop stability and is covered in the next section. the steady state evaluation can be simplified with the use of the final value theorem associated with laplace. this theorem permits finding the steady state system error q e (s) resulting from the input q i (s) without transforming back to the time domain. 3 lim [ q (t)] = lim [s q e (s)] ( 10 ) t s o where simply stated e (s) 1 1 g(s) h(s) i (s) ( 11 ) the input signal q i (s) is characterized as follows: step position: q i (t) = c p t 0 ( 12 ) or, in laplace notation: ( 13 ) i (s) c p s where c p is the magnitude of the phase step in radians. this corresponds to shifting the phase of the incoming reference signal by c p radians: step velocity: q i (t) = c v t t 0 ( 14 ) or, in laplace notation: ( 15 ) i (s) c v s 2 where c v is the magnitude of the rate of change of phase in radians per second. this corresponds to inputting a frequency that is different than the feedback portion of the vco frequency. thus, c v is the frequency difference in radians per second seen at the phase detector. step acceleration: q i (t) = c a t 2 t 0 ( 16 ) or, in laplace notation: ( 17 ) i (s) 2c a s 3 c a is the magnitude of the frequency rate of change in radians per second per second. this is characterized by a time variant frequency input. typical loop g(s) h(s) transfer functions for types 1, 2, and 3 are: type 1 ( 18 ) g(s) h(s) k s(s a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3 motorola semiconductor application information type 2 ( 19 ) g(s) h(s) k(s a) s 2 type 3 ( 20 ) g(s) h(s) k(s a)(s b) s 3 the final value of the phase error for a type 1 system with a step phase input is found by using equations 11 and 13. ( 21 ) e (s) 1 1 k s(s a) c p s (s a)c p (s 2 as k) e (t ) lim s s a s 2 as k c p 0 ( 22 ) s o thus, the final value of the phase error is zero when a step position (phase) is applied. similarly, applying the three inputs into type 1, 2, and 3 systems and utilizing the final value theorem, the following table can be constructed showing the respective steady state phase errors. table 1. steady state phase errors for various system types type 1 type 2 type 3 step position zero zero zero step velocity constant zero zero step acceleration continually increasing constant zero a zero phase error identifies phase coherence between the two input signals at the phase detector. a constant phase error identifies a phase differential between the two input signals at the phase detector. the magnitude of this differential phase error is proportional to the loop gain and the magnitude of the input step. a continually increasing phase error identifies a time rate change of phase. this is an unlocked condition for the phase loop. using table 1, the system type can be determined for specific inputs. for instance, if it is desired for a pll to track a reference frequency (step velocity) with zero phase error, a minimum of type 2 is required. stability the root locus technique of determining the position of system poles and zeroes in the s-plane is often used to graphically visualize the system stability. the graph or plot illustrates how the closed loop poles (roots of the characteristic equation) vary with loop gain. for stability, all poles must lie in the left half of the s-plane. the relationship of the system poles and zeroes then determine the degree of stability. the root locus contour can be determined by using the following guidelines. 2 rule 1 the root locus begins at the poles of g(s) h(s) (k = 0) and ends at the zeroes of g(s) h(s) (k = ), where k is loop gain. rule 2 the number of root loci branches is equal to the number of poles or number of zeroes, whichever is greater. the number of zeroes at infinity is the difference between the number of finite poles and finite zeroes of g(s) h(s). rule 3 the root locus contour is bounded by asymptotes whose angular position is given by: ( 23 ) (2n 1) #p #z ;n 0, 1, 2, ... where #p (#z) is the number of poles (zeroes). rule 4 the intersection of the asymptotes is positioned at the center of gravity c.g.: ( 24 ) c.g. p z #p #z where s p ( s z) denotes the summation of the poles (zeroes). rule 5 on a given section of the real axis, root loci may be found in the section only if the #p + #z to the right is odd. rule 6 breakaway points from negative real axis is given by: ( 25 ) dk ds 0 again, where k is the loop gain variable factored from the characteristic equation. example: the root locus for a typical loop transfer function is found as follows: ( 26 ) g(s) h(s) k s(s 4) the root locus has two branches (rule 2) which begin at s = 0 and s = 4 and ends at the two zeroes located at infinity (rule 1). the asymptotes can be found according to rule 3. since there are two poles and no zeroes, the equation becomes: ( 27 ) 2n 1 2 2 for n 0 3 2 for n 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4 motorola semiconductor application information the position of the intersection according to the rule 4 is: ( 28 ) s p z #p #z ( 4 0) (0) 2 0 s 2 the breakaway point, as defined by rule 6, can be found by first writing the characteristic equation. ( 29 ) c.e. 1 g(s) h(s) 0 1 k s(s 4) s 2 4s k 0 now solving for k yields k = s 2 4s ( 30 ) taking the derivative with respect to s and setting it equal to zero, then determines the breakaway point. ( 31 ) dk ds d ds ( s 2 4s) ( 32 ) dk ds 2s 4 0 or s = 2 ( 33 ) is the point of departure. using this information, the root locus can be plotted as in figure 3. the second order characteristic equation, given by equation 29, has be normalized to a standard form 2 s 2 + 2 zw n s + w 2 n ( 34 ) where the damping ratio x = cos f (0 f 90 ) and w n is the natural frequency as shown in figure 3. figure 3. type 1 second order root locus contour !'% " %) '+ &+ #'"' p w 8 f s &+ #'"' p % *+ #" !' 4 w the response of this type 1, second order system to a step input, is shown in figure 4. these curves represent the phase response to a step position (phase) input for various damping ratios. the output frequency response as a function of time to a step velocity (frequency) input is also characterized by the same set of figures. w 8 = figure 4. type 1 second order step response q 9 =!"% ,"('#('%&#"!& z the overshoot and stability as a function of the damping ratio x is illustrated by the various plots. each response is plotted as a function of the normalized time w n t. for a given x and a lock-up time t, the w n required to achieve the desired results can be determined. example: assume x = 0.5 error < 10% for t > 1ms from x = 0.5 curve error is less than 10% of final value for all time greater than w n t = 4.5. the required w n can then be found by: w n t = 4.5 ( 35 ) or ( 36 ) n 4.5 t 4.5 0.001 4.5krad s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5 motorola semiconductor application information x is typically selected between 0.5 and 1 to yield optimum overshoot and noise performance. example: another common loop transfer function takes the form: ( 37 ) g(s) h(s) (s a)k s 2 this is a type 2 second order system. a zero is added to provide stability. (without the zero, the poles would move along the j w axis as a function of gain and the system would at all times be oscillatory in nature.) the root locus shown in figure 5 has two branches beginning at the origin with one asymptote located at 180 degrees. the center of gravity is s = a; however, with only one asymptote, there is no intersection at this point. the root locus lies on a circle centered at s = a and continues on all portions of the negative real axis to left of the zero. the breakaway point is s = 2a. figure 5. type 2 second order root locus contour w 8 f s - 4 w - ? 38. 1 2 for a type 2 second order 1 system. phase-locked loop design example the design of a pll typically involves determining the type of loop required, selecting the proper bandwidth, and establishing the desired stability. a fundamental approach to figure 6. type 2 second order step response w 8 = q 9 =!"% ,"('#('%$(!+ z these design constraints is now illustrated. it is desired for the system to have the following specifications: output frequency 2.0mhz to 3.0mhz frequency steps 100khz phase coherent frequency output e lock-up time between channels 1ms overshoot <20% note: these specifications characterize a system function similar to a variable time base generator or a frequency synthesizer from the given specifications, the circuit parameters shown in figure 7 can now be determined. the devices used to configure the pll are: frequency-phase detector mc4044/4344 voltage controlled multivibrator (vcm) mc4024/4324 programmable counter mc4016/4316 the forward and feedback transfer functions are given by: g(s) = k p k f k o h(s) = k n ( 40 ) where k n = 1/n ( 41 ) the programmable counter divide ratio k n can be found from equation 3. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6 motorola semiconductor application information figure 7. phase-locked loop circuit parameters f i phase detector k p programmable counter k n filter k f vcm k o f o ( 42 ) n min f o min f i f o min f step 2mhz 100khz 20 ( 43 ) n max f o max f step 3mhz 100khz 30 ( 44 ) k n 1 20 to 1 30 a type 2 system is required to produce a phase coherent output relative to the input (see table 1). the root locus contour is shown in figure 5 and the system step response is illustrated by figure 6. the operating range of the mc4024/4324 vcm must cover 2mhz to 3mhz. selecting the vcm control capacitor according to the rules contained on the data sheet yields c = 100pf. the desired operating range is then centered within the total range of the device. the input voltage versus output frequency is shown in figure 8. figure 8. mc4324 input voltage versus output frequency (100pf feedback capacitor) 1 9>= "('#(' %$(!+ @ ) 38 !#(')" ')" '& ) )/. a a a a the transfer function of the vcm is given by: ( 45 ) k o k v s where k v is the sensitivity in radians per second per volt. from the curve in figure 8, k v is found by taking the reciprocal of the slope. k v 4mhz 1.5mhz 5v 3.6v 2 rad s v k v = 11.2 x 10 6 rad/s/v ( 46 ) thus k o 11.2 x10 6 s rad s v ( 47 ) the s in the denominator converts the frequency characteristics of the vcm to phase, i.e., phase is the integral of frequency. the gain constant for the mc4044/4344 phase detector is found by 5 k p dfhigh uflow 2(2 ) 2.3v 0.9v 4 0.111v rad ( 48 ) since a type 2 system is required (phase coherent output) the loop transfer function must take the form of equation 19. the parameters thus far determined include k p , k o , k n leaving only k f as the variable for design. writing the loop transfer function and relating it to equation 19 g(s)h(s) k p k v k n k f s k(s a) s 2 ( 49 ) thus, k f must take the form k f s a s ( 50 ) in order to provide all of the necessary poles and zeroes for the required g(s) h(s). the circuit shown in figure 9 yields the desired results. figure 9. active filter design % % b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7 motorola semiconductor application information k f is expressed by k f r 2 cs 1 r 1 cs for largea ( 51 ) where a is voltage gain of the amplifier. r 1 , r 2 , and c are then the variables used to establish the overall loop characteristics. the mc4044/4344 provides the active circuitry required to configure the filter k f . an additional low current high b buffering device or fet can be used to boost the input impedance, thus minimizing the leakage current from the capacitor c between sample updates. as a result, longer sample periods are achievable. since the gain of the active filter circuitry in the mc4044/4344 is not infinite, a gain correction factor k c must be applied to k f in order to properly characterize the function. k c is found experimentally to be k c = 0.5. k fc k f k c 0.5 r 2 cs 1 r 1 cs ( 52 ) (for large gain, equation 51 applies.) the pll circuit diagram is shown in figure 11 and its laplace representation in figure 10. the loop transfer function is g(s)h(s) k p (0.5) r 2 cs 1 r 1 cs k v s 1 n ( 53 ) g(s) h(s) = k p k fc k o k n ( 54 ) the characteristic equation takes the form ( 55 ) c.e. 1 g(s) h(s) 0 s 2 0.5 k p k v r 2 r 1 n s 0.5 k p k v r 1 cn relating equation 55 to the standard form given by equation 34 s 2 0.5 k p k v r 2 r 1 n s 0.5 k p k v r 1 cn = s 2 + 2 zw n s + w n 2 ( 56 ) equating like coefficients yields 0.5 k p k v r 1 cn n 2 ( 57 ) and 0.5 k p k v r 2 r 1 n 2 n ( 58 ) with the use of an active filter whose open loop gain (a) is large (k c = 1), equations 57 and 58 become k p k v r 1 cn n 2 ( 59 ) k p k v r 2 r 1 n 2 n ( 60 ) the percent overshoot and settling time are now used to determine w n . from figure 6, it is seen that a damping ratio z = 0.8 will produce a peak overshoot less than 20% and will settle within 5% at w n t = 4.5. the required lock-up time is 1ms. n 4.5 t 4.5 0.001 4.5krad s ( 61 ) rewriting equation 57 r 1 c 0.5 k p k v n 2 n ( 62 ) (0.5) (0.111) (11.2 x 10 6 ) (4500) 2 (30) r 1 c = 0.00102 (maximum overshoot occurs at n max which is minimum loop gain) then let c = 0.5 m f r 1 0.00102 0.5 x 10 -6 2.04k use r 1 = 2k w k f r 2 cs 1 2r 1 cs figure 10. laplace representation of diagram in figure 11. k p = 0.111v/rad q o (s) q i (s) + k n 1 20 to 1 30 k o 11.2 s *10 6 rad s v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8 motorola semiconductor application information figure 11. circuit diagram of type 2 phase-locked loop # # # # # # # # : ) 1 9 1 3 % 5 % 5 % ) #& 089=0< :-;=< 0?=0;8-6 =9 =20 5 r 1 is typically selected greater than 1k w . solving for r 2 in equation 58 r 2 2 n r 1 n k p k v (0.5) 2 c n ( 63 ) use r 2 = 680 w = 711 w 2(0.8) (0.5 x 10 -6 )(4.5k) all circuit parameters have now been determined and the pll can be properly configured. since the loop gain is a function of the divide ratio k n , the closed loop poles will vary its position as k n varies. the root locus shown in figure 12 illustrates the closed loop pole variation. the loop was designed for the programmable counter n = 30. the system response for n = 20 exhibits a wider bandwidth and larger damping factor, thus reducing both lock-up time and percent overshoot (see figure 14). figure 12. root locus variation 5 n = 30 w n = 4.61krad/s z = 0.785 n = 20 w n = 5.64krad/s z = 0.961 note: the type 2 second order loop was illustrated as a design sample because it provides excellent performance for both type 1 and 2 applications. even in systems that do not require phase coherency, a type 2 loop still offers an optimum design. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9 motorola semiconductor application information experimental results figure 13 shows the theoretical transient frequency response of the previously designed system. the curve n = 30 illustrates the frequency response when the programmable counter is stepped from 29 to 30, thus producing a change in the output frequency from 2.9mhz to 3.0mhz. an overshoot of 18% is obtained and the output frequency is within 5khz of the final value one millisecond after the applied step. the curve n = 20 illustrates the output frequency change as the programmable counter is stepped from 21 to 20. since the frequency is proportional to the vcm control voltage, the pll frequency response can be observed with an oscilloscope by monitoring pin 2 of the vcm. the average frequency response as calculated by the laplace method is found experimentally by smoothing this voltage at pin 2 with a simple rc filter whose time constant is long compared to the phase detector sampling rate, but short compared to the pll response time. with the programmable counter set at 29 the quiescent control voltage at pin 2 is approximately 4.37 volts. upon changing the counter divide ratio to 30, the control voltage increases to 4.43 volts as shown in figure 14. a similar transient occurs when stepping the programmable counter from 21 to 20. figure 14 illustrated that the experimental results obtained from the configured system follows the predicted results shown in figure 13. linearity is maintained for phase errors less than 2 p , i.e. there is no cycle slippage at the phase detector. figure 13. frequency-time response "('#('%$(!+ @ ' 7< ! ! &=0: 8:>= ! &'## %" '" ! &'## %" '" figure 14. vcm control voltage (frequency) transient ) ) ) .7 7< .7 ) ) ) !&'##%" '" !&'##%" '" figure 15 is a theoretical plot of the vcm control voltage transient as calculated by a computer program. the computer program is written with the parameters of equations 58 and 59 (type 2) as the input variables and is valid for all damping ratios of z 1.0. the program prints or plots control voltage transient versus time for desired settings of the programmable counter. the lock-up time can then be readily determined as the various parameters are varied. (if stepping from a higher divide ratio to a lower one, the transient will be negative.) figures 14 and 15 also exhibit a close correlation between experimental and analytical results. summary this application note describes the basic control system techniques required for phase-locked loop design. criteria for the selection of the optimum type of loop and methods for establishing the desired performance characteristics are presented. a design example is illustrated in a step-by-step approach along with the comparison of the experimental and analytical results. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10 motorola semiconductor application information figure 15. vcm control signal transient *the parameters listed below apply to the following plot phase detector gain constant vcm gain constant filter input resistor filter feedback resistor filter capacitor divider value reference frequency output frequency change p1 = 0.111 volts per radian v1 =1.12 e+7 rad per volt r1 = 3900 ohms (r1 c = 2k) r2 = 680 ohms c1 = 0.5 microfarads n1-n2 = 29 30 f1 = 100000 cps f5 = 100000 cps p2 = 0.111 v2 = 1.12 e+7 r3 = 3900 (r1 c = 2k) r4 = 680 c2 = 0.5 n3-n4 = 21 20 f2 (f6) = 100000 (100000) p l o t o f f u n c t i o n s bottom = 0 . 0015 right = 0.12 increment = 0 . 0005 increment = 0.002 top = 0 left = 0 for t: for fcts: (note: y(t) is `+', z(t) is `*', and ` ' is common) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11 motorola semiconductor application information bibliography 1. topic: type two system analysis gardner, f. m., phase lock techniques , wiley, new york, second edition, 1967 2. topic: root locus techniques kuo, b. c., automatic control systems , prentice-hall, inc., new jersey, 1962 3. topic: laplace techniques mccollum, p. and brown, b., laplace transform tables and theorems , holt, new york, 1965 4. topic: type one system analysis truxal, j. g., automatic feedback control system synthesis , mcgraw-hill, new york, 1955 5. topic: phase detector gain constant delaune, jon, mttl and mecl avionics digital frequency synthesizer , an532 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 12 motorola semiconductor application information motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation o r guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in dif ferent applications. all operating parameters, including atypicalso must be validated for each customer application by customer's tec hnical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or auth orized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any othe r application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the desig n or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employe r. literature distribution centers: usa: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. AN535/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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